Pulse Width Modulation (PWM) On A9 Core and Device Trees

Discussion in 'UDOO NEO' started by fireblade, Feb 5, 2018.

  1. fireblade

    fireblade UDOOer

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    Im looking to control, at least 5, of the pwm outputs from linux but cannot see how to configure this

    the simplest option being like the example on https://www.udoo.org/docs-neo/Hardware_&_Accessories/GPIO.html

    with pwm 1-6 connected to internal pins 3-9

    currently doing

    Code:
    echo 0 > /sys/class/pwm/pwmchip0/export
    gets
    Code:
    -bash: /sys/class/pwm/pwmchip0/export: No such file or directory
    and the pwm dir is empty

    Code:
    ls -l /sys/class/pwm/
    total 0
    
    ive disabled the m4
    Code:
    root@udooneo:~# sudo udoom4ctl status
    false
    
    the device tree editor is of no help as it doesn't control internal pins even with m4 disabled and only allows pwm 2 and 5

    looking at the /sys/class/gpio dir disabling the m4 doesn't seem to have set all pins back to control by the A9
    e.g pin 8 which is only associated with gpio 105 in (https://www.udoo.org/docs-neo/Hardware_&_Accessories/GPIO.html) doesn't exist

    Code:
    ls /sys/class/gpio/gpio105
    ls: cannot access /sys/class/gpio/gpio105: No such file or directory
    
    is there some other setting needed to reassign the internal pins back to the a9 in addition to disabling the m4?
     
  2. fireblade

    fireblade UDOOer

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    after rebooting i now appear to have access to two pwm

    Code:
    root@udooneo:~# ls -l  /sys/class/pwm/
    total 0
    lrwxrwxrwx 1 root root 0 Feb  5 16:53 pwmchip0 -> ../../devices/soc0/soc.0/2200000.aips-bus/22ac000.pwm/pwm/pwmchip0
    lrwxrwxrwx 1 root root 0 Feb  5 16:53 pwmchip1 -> ../../devices/soc0/soc.0/2200000.aips-bus/22b0000.pwm/pwm/pwmchip1
    
    but still need to "enable" another 3
     
  3. fireblade

    fireblade UDOOer

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    Having done some further examination it looks like this is configured via dts/dtsi file isn (linux_kernel/arch/arm/boot/dts/)
    and compiled dtb files in /boot/dts (or boot/dts-overlay)

    looking at imx6sx-udoo-neo-externalpins.dtsi and imx6sx-udoo-neo-m4.dtsi
    the pwm appear to be disabled whether the m4 is enabled or not

    but as there seem to be two pwm enabled im not sure where this is done

    can anyone tell me what i need to do with the dts files to ensure that pwm 1-5 are enabled on the a9 and connected to internal pins 3-7 see (https://www.udoo.org/docs-neo/img/gionji/DOCS_internal_pinout.PNG)
     
  4. jas-mx

    jas-mx Active Member

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    You need to look a the external pinout diagram , however even then you will find some of the PWM won't be available as they are assigned to other ports ie I2C4 which I'm not sure you can disable or not through the editor. You can manually hack the dts/dtsi files to suit your requirements/setup and compile them manually.
     
  5. fireblade

    fireblade UDOOer

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    I realise that, its the changes to the dts files probably (
    linux_kernel/arch/arm/boot/dts/imx6sx-udoo-neo-externalpins.dtsi)
    that need making im unsure about

    also i cant see anything that confirms which pwmchip0 etc actually is


    it appears from comparing (linux_kernel/arch/arm/boot/dts/imx6sx.dtsi)
    Code:
                pwm7: pwm@022ac000 {
                    compatible = "fsl,imx6sx-pwm", "fsl,imx27-pwm";
                    reg = <0x022ac000 0x4000>;
                    interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>;
                    clocks = <&clks IMX6SX_CLK_PWM7>,
                         <&clks IMX6SX_CLK_PWM7>;
                    clock-names = "ipg", "per";
                    #pwm-cells = <2>;
                };
    
                pwm8: pwm@0022b0000 {
                    compatible = "fsl,imx6sx-pwm", "fsl,imx27-pwm";
                    reg = <0x0022b0000 0x4000>;
                    interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
                    clocks = <&clks IMX6SX_CLK_PWM8>,
                         <&clks IMX6SX_CLK_PWM8>;
                    clock-names = "ipg", "per";
                    #pwm-cells = <2>;
    };
    and
    Code:
    fireblade@udooneo:~$ ls -l /sys/class/pwm/pwmchip0/
    total 0
    lrwxrwxrwx 1 root root    0 Feb  5 16:54 device -> ../../../22ac000.pwm
    --w------- 1 root root 4096 Feb  6 17:13 export
    -r--r--r-- 1 root root 4096 Feb  5 16:54 npwm
    drwxr-xr-x 2 root root    0 Feb  5 16:54 power
    drwxr-xr-x 3 root root    0 Feb  6 17:14 pwm0
    lrwxrwxrwx 1 root root    0 Feb  5 16:54 subsystem -> ../../../../../../../class/pwm
    -rw-r--r-- 1 root root 4096 Feb  5 16:54 uevent
    --w------- 1 root root 4096 Feb  5 16:54 unexport
    fireblade@udooneo:~$ ls -l /sys/class/pwm/pwmchip1/
    total 0
    lrwxrwxrwx 1 root root    0 Feb  6 17:14 device -> ../../../22b0000.pwm
    --w------- 1 root root 4096 Feb  6 17:14 export
    -r--r--r-- 1 root root 4096 Feb  6 17:14 npwm
    drwxr-xr-x 2 root root    0 Feb  6 17:14 power
    drwxr-xr-x 3 root root    0 Feb  6 17:14 pwm0
    lrwxrwxrwx 1 root root    0 Feb  6 17:14 subsystem -> ../../../../../../../class/pwm
    -rw-r--r-- 1 root root 4096 Feb  6 17:14 uevent
    --w------- 1 root root 4096 Feb  6 17:14 unexport
    
    that pwmchip0 and 1 are pwms 7 and 8 respectively
     
    Last edited: Feb 14, 2018
  6. fireblade

    fireblade UDOOer

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    using dtc i can edit the dtb files to remove the disabled flag
    but i cant get the other pwm to appear in /sys/class/pwm , /sys/devices/soc0/soc.0/2200000.aips-bus/ or /sys/devices/soc0/soc.0/2000000.aips-bus/

    but can be seen in /proc/device-tree/soc/aips-bus@02000000/ and /proc/device-tree/soc/aips-bus@02200000/
     
  7. hiten

    hiten UDOOer

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    hello, can anyone find the solution ??
     
  8. waltervl

    waltervl UDOOer

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