How to enable the 1588 ptp clock?

Discussion in 'UDOO QUAD' started by jeffrey830818, Jun 7, 2017.

  1. jeffrey830818

    jeffrey830818 New Member

    Joined:
    Feb 26, 2016
    Messages:
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    Hi there,
    I'm using UDOO quad and I stuck in this 1588 issue two weeks.
    My timestamp wasn't counting, I want to put timestamp in my ethernet packet but the program caught the same timestamp again and again. I read all of the documents about this issue but still confused.
    [​IMG]
    [​IMG]


    Device tree:
    imx6q-udoo {
    pinctrl_hog: hoggrp {
    fsl,pins = <
    // Internal GPIOs
    MX6QDL_PAD_NANDF_D4__GPIO2_IO04 0x80000000 // 5v enable
    MX6QDL_PAD_NANDF_CS0__GPIO6_IO11 0x80000000 // Vtt enable

    MX6QDL_PAD_DISP0_DAT5__GPIO4_IO26 0x80000000 // Debug UART (J18)

    MX6QDL_PAD_GPIO_17__GPIO7_IO12 0x80000000 // USB hub reset
    MX6QDL_PAD_NANDF_CS2__CCM_CLKO2 0x130b0 // USB hub clock
    MX6QDL_PAD_EIM_WAIT__GPIO5_IO00 0xb0b1 // USB OTG select

    MX6QDL_PAD_NANDF_D5__GPIO2_IO05 0x80000000 // SD card power
    MX6QDL_PAD_SD3_DAT5__GPIO7_IO00 0x80000000 // SD card detect

    MX6QDL_PAD_GPIO_16__GPIO7_IO11 0xb0b1 // SAM3X OTG vbus_en
    MX6QDL_PAD_SD4_DAT7__GPIO2_IO15 0x80000000 // SAM3X usb host
    MX6QDL_PAD_GPIO_3__GPIO1_IO03 0x30b1 // Arduino pinout pin 12

    MX6QDL_PAD_GPIO_2__GPIO1_IO02 0x80000000 // LVDS panel on (CN13)
    MX6QDL_PAD_GPIO_4__GPIO1_IO04 0x80000000 // LVDS backlight on (CN13)

    MX6QDL_PAD_CSI0_DAT18__GPIO6_IO04 0x1f071 // CSI camera enable (CN11)
    MX6QDL_PAD_CSI0_DAT19__GPIO6_IO05 0x1f071 // CSI camera reset (CN11)
    MX6QDL_PAD_CSI0_MCLK__CCM_CLKO1 0x130b0 // CSI master clock (CN11)

    >;
    };

    pinctrl_enet: enetgrp {
    fsl,pins = <
    MX6QDL_PAD_RGMII_RXC__RGMII_RXC 0x1b0b0
    MX6QDL_PAD_RGMII_RD0__RGMII_RD0 0x1b0b0
    MX6QDL_PAD_RGMII_RD1__RGMII_RD1 0x1b0b0
    MX6QDL_PAD_RGMII_RD2__RGMII_RD2 0x1b0b0
    MX6QDL_PAD_RGMII_RD3__RGMII_RD3 0x1b0b0
    MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL 0x1b0b0
    MX6QDL_PAD_RGMII_TXC__RGMII_TXC 0x1b0b0
    MX6QDL_PAD_RGMII_TD0__RGMII_TD0 0x1b0b0
    MX6QDL_PAD_RGMII_TD1__RGMII_TD1 0x1b0b0
    MX6QDL_PAD_RGMII_TD2__RGMII_TD2 0x1b0b0
    MX6QDL_PAD_RGMII_TD3__RGMII_TD3 0x1b0b0
    MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL 0x1b0b0
    MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK 0x1b0b0
    MX6QDL_PAD_ENET_MDIO__ENET_MDIO 0x1b0b0
    MX6QDL_PAD_ENET_MDC__ENET_MDC 0x1b0b0
    MX6QDL_PAD_EIM_D23__GPIO3_IO23 0x80000000 /* RGMII_nRST */
    MX6QDL_PAD_EIM_EB3__GPIO2_IO31 0x80000000 /* EN_ETH_PWR */
    >;
    };




    Best Regards,

    Jeffrey.
     

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