Hi all, I am new to Udoo. I am playing around with my MAX10M50 FPGA EK. The kit has one specific FFC connector designed for Udoo OV5640 camera module. I checked the pinouts, they match well. Below you can find the detail about the EK. https://www.altera.com/products/boards_and_kits/dev-kits/altera/kit-max-10m50-evaluation.html J3 is for the Udoo camera. However I did not find any example Verilog source file or relative IP to drive the camera on Altera's website. I am wondering if anyone here has experience on working with FPGA and could give me some advise. Thanks!